This invention relates to trench optical devices formed in semiconductor substrates, and more particularly to one or more trench lateral p-i-n photodiodes alone or in an array in a photodetector.
Trench lateral p-i-n photodiodes are semiconductor devices including one or more photodiodes each of which comprises a sandwich of an anode, an intrinsic region and a cathode. The anode comprises a region composed of a material such as polysilicon doped with a P-type dopant and the cathode comprises a region composed of a material such as polysilicon doped with an N-type dopant. The intrinsic region comprises a semiconductor region which is lightly doped with a dopant such as a light doping with a P-type dopant. When a high intensity light signal impinges on one or more photodiodes alone or in a photodetector, each photodiode conducts current in reverse mode, or in other words, from cathode to anode generating an output voltage across a load resistor (not shown) between the cathode and the anode. When the light signal disappears or weakens to a low intensity, the current generated by the photodiode ceases, and the lack of current decreases the voltage appearing across the load resistor.
In summary, a p-i-n semiconductor diode is formed with an intrinsic (i) semiconductor region located between an anode which comprises a P-type region (doped with a P type dopant) and a cathode which comprises an N-type region (doped with an N type dopant).
Referring to a commonly assigned U.S. Pat. No. 6,177,289 of Crow et al. entitled. “Lateral Trench Optical Detectors,” a lateral p-i-n photodiode is described which is formed by alternating parallel N-type trenches and P-type trenches formed in an intrinsic “i” semiconductor which is lightly doped. U.S. Pat. No. 6,538,299 of Kwark entitled “Silicon-On-Insulator (SOI) Trench Photodiode” U.S. Pat. No. 6,451,702 of Yang et al. entitled “Methods for Forming Lateral Trench Optical Detectors,” and U.S. Pat. No. 6,667,528 of Cohen et al. entitled “Silicon-On-Insulator (SOI) Lateral Photodetector with a Reflecting Mirror and Backside Contact and Method for Forming the Same”, which are commonly assigned, describe aspects of lateral trench photodetectors.
Publications pertinent to the subject of deep trench, lateral p-i-n photodiodes include M. Yang et al. “A High-Speed, High-Sensitivity Silicon Lateral Trench Photodetector,” IEEE electron device letters, vol. 23, pp 395–397 (2002); and M. Yang et al. “High Speed Silicon Lateral Trench Detector on SOI Substrate,” IEDM, pp 547–550 (2001). Such photodiodes can be employed as either individual diodes for detecting pixels or can be employed in an array of distributed P and N regions which are interconnected to provide combined signals in response to an optical beam data received by elements of the array to provide a signal with enhanced amplitude. For example such photodetectors can be employed in optical data transmission systems.
FIG. 1A shows a schematic, elevational, sectional view taken along section line 1A—1A in FIG. 1B of a prior art type of a single lateral p-i-n photodiode 6 which is a component of a photodetector 10.
FIG. 1B is a plan (top) view of a layout of the photodetector 10 which includes an interconnected parallel array of photodiodes including the photodiode 6 of FIG. 1A taken along line 1B—1B in FIG. 1A.
FIG. 1A is an enlarged sectional elevation of the single lateral p-i-n photodiode 6, which is shown there as a stand alone device, but which is shown as part of a parallel array of interconnected photodiodes in FIG. 1B.
In FIG. 1A, the single lateral p-i-n photodiode 6 is formed in a conductive semiconductor substrate 12, comprising a lightly doped with P-type dopant forming a central intrinsic “i” region 11. Side views of two parallel deep trenches 7 and 8 having the same width of WN are shown formed in the substrate 12 on either side of the central intrinsic “i” region 11. On left side of the central intrinsic “i” region 11 in FIG. 1A, the deep trench 7 is filled with an anode 22 comprising polysilicon doped with a P-type dopant. To the right of the central intrinsic “i” region 11 in FIG. 1A, the deep trench 8 is filled with a cathode 26 comprising polysilicon doped with an N-type dopant, as will be well understood by those skilled in the art of lateral trench photo-detectors that are formed in semiconductors. Surrounding the anode 22 is a P-type doped outdiffusion region 23; and surrounding the cathode 26 is an N-type doped outdiffusion region 27. Contact 28P, that is formed atop of the anode 22, is connected to ground by a lead line 30. Contact 28N, which is formed on top of cathode 26, is connected to another lead line 31. A pad layer 14 is formed on top of the substrate 12, aside from the contacts 28P and 28N. As described above, light passing through the pad layer 14 into the intrinsic region 11 are generates holes “h+” and electrons “e−”. The holes migrate to the P-type doped anode 22 and electrons migrate to the N-type doped cathode 26 due to the applied voltage VBIAS as indicated in FIG. 1A. Alternatively, the substrate 12 can be lightly doped with N-type dopant.
In FIG. 1B, the anodes 22 are connected to the contact 28P as in FIG. 1A, and the cathodes 26 are connected to the contact 28N. The anodes 22 and cathodes 26 alternate across the substrate 12 with anodes 22 alternating with cathodes 26 and with intrinsic regions 11 located between anodes 22 and cathodes 26. The p-i-n photodiode of FIG. 1A is shown on the left side of FIG. 1B.
FIG. 1C shows a perspective view of the photodetector 10 of FIG. 1B with the array of a set of p-i-n photodiodes formed in a P-doped semiconductor substrate 12. The central intrinsic regions 11 are located between pairs of P-type doped polysilicon cathodes 22 and N-type doped polysilicon anodes 26, both of which are relatively narrow having a width of WN.
FIG. 1D shows a perspective view of the device of FIG. 1B formed in an SOI version of the photodetector 10 with a P-doped semiconductor layer 12 formed on a Buried OXide (BOX) layer 113 formed on a substrate 112. As shown in FIG. 2C, the intrinsic regions 11 are located between pairs of narrow P-type doped polysilicon cathodes 22 and narrow N-type doped polysilicon anodes 23.
The first deep trench 7 and the second deep trench 8, which are formed in parallel with each other in the intrinsic region “i” in substrate 12, have equal narrow widths of WN (WNARROW) as shown in FIGS. 1A and 1B. There are two primary methods in prior art to form the alternating N-type doped and P-type doped trenches 7 and 8. Both methods are complex and costly because both methods require at least two mask levels, two hardmask processes, two planarization processes, and multiple etching processes.
First Prior Art Process
1. Start with a semiconductor type of substrate with a planar surface.
2. Form a pad layer atop the semiconductor substrate and form a first hardmask layer atop the pad layer. As indicated above, in the final device, light passes through the pad layer 14 into the intrinsic region 11 generating holes “h+” and electrons “e−”.
3. Form a first photoresist layer atop the hardmask layer.
4. Pattern the photoresist layer by using a first mask.
5. Transfer the pattern from the photoresist layer to the hardmask layer.
6. Strip the photoresist.
7. Perform an etch process through the patterned hard-mask to form deep trenches having the same dimension in the substrate.
8. Strip the remaining hardmask.
9. Fill all of the trenches with a sacrificial material such as BSG (BoroSilicateGlass).
10. Form a second hardmask.
11. Form a second photoresist layer.
12. Pattern the second photoresist layer to expose the top of the every other trench by using a second mask. Transfer the pattern from the second photoresist layer to the second hardmask layer.
13. Strip the second photoresist layer.
14. Remove the sacrificial material from every other trench through openings in the second hardmask creating a first set of empty trenches leaving a second set of full trenches therebetween.
15. Strip the remaining second hardmask.
16. Fill the first set of empty trenches with a first layer of polysilicon doped with first type of P or N type dopant.
17. Perform a first planarization step (e.g., CMP) to planarize the first layer of polysilicon and expose the sacrificial material. Remove the sacrificial material from the other set of trenches.
18. Fill empty trenches with polysilicon with other type of P type or N type dopant.
19. Perform a second planarization step (e.g. CMP) to remove excess polysilicon.
20. Form contacts.
This first prior art process has several disadvantages. First, it is complex and costly since it requires at least two mask levels, two hardmask deposition steps, two planarization steps, and multiple pattern transfer steps to form the alternating N-type doped and P-type doped trenches. Second, the alignment issue between the second mask level and the first mask level results in difficulties in process control. Third, filling the trench with sacrificial material and removing the sacrificial material from a deep trench twice consumes a large quantity of chemicals and requires a very long process time. Finally, there is a defect issue associated with the complex process, which causes device performance and reliability degradation as well as product yield loss.
Second Prior Art Process
1. Start with a semiconductor or SOI type of substrate with a planar surface.
2. Form a pad layer atop the semiconductor substrate and form a first hardmask layer atop the pad layer. As indicated above, in the final device, light passes through the pad layer 14 into the intrinsic region 11 generating holes “h+” and electrons “e−”.
3. Form a first photoresist layer atop the hardmask layer.
4. Pattern the photoresist layer by using a first mask for forming the first type of deep trenches.
5. Transfer the pattern from the photoresist layer to the hardmask layer.
6. Strip the photoresist.
7. Perform a first deep trench etch process through the patterned hardmask to form a first type of deep trenches.
8. Strip the first remaining hardmask.
9. Fill the first type of trench with a first polysilicon doped with a first type of dopants.
10. Planarize the first layer of polysilicon.
11. Form a second hardmask layer. Form a second photoresist layer atop the hardmask layer.
12. Pattern the photoresist layer by using a second mask for forming the other type of deep trenches.
13. Transfer the pattern from the photoresist layer to the hardmask layer.
14. Strip the photoresist.
15. Perform a second deep trench etch process through the second patterned hardmask to form a second type of deep trenches.
16. Strip the second remaining hardmask.
17. Fill the empty second set of trenches with polysilicon with the other type of P or N type dopant.
18. Perform a second planarization step to remove excess polysilicon.
19. Form contacts.
The second prior art process also has several disadvantages. First, it is complex and costly since it requires at least two mask levels, two hardmask deposition steps, two planarization steps, and multiple pattern transfer steps to form the alternating N-type doped and P-type doped trenches. Second, the alignment issue between the second mask level and the first mask level results in difficulties in process control. Third, forming deep trenches is a very time-consuming process, so forming two types of deep trenches separately adds considerable process complexity and significant cost. Finally, there is a defect issue associated with the complex process, which causes device performance and reliability degradation as well as product yield loss.